Spike, a top rated RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts. Spike is highly rated on Github with over 1400 stars.
Spike supports the following RISC-V ISA features:
- RV32I and RV64I base ISAs, v2.1
- RV32E and RV64E base ISAs, v1.9
- Zifencei extension, v2.0
- Zicsr extension, v2.0
- M extension, v2.0
- A extension, v2.1
- F extension, v2.2
- D extension, v2.2
- Q extension, v2.2
- C extension, v2.0
- Zbkb, Zbkc, Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh scalar cryptography extensions (Zk, Zkn, and Zks groups), v1.0
- Zkr virtual entropy source emulation, v1.0
- V extension, v1.0 (requires a 64-bit host)
- P extension, v0.9.2
- Zba extension, v1.0
- Zbb extension, v1.0
- Zbc extension, v1.0
- Zbs extension, v1.0
- Zfh and Zfhmin half-precision floating-point extensions, v1.0
- Zfinx extension, v1.0
- Zmmul integer multiplication extension, v1.0
- Zicbom, Zicbop, Zicboz cache-block maintenance extensions, v1.0
- Conformance to both RVWMO and RVTSO (Spike is sequentially consistent)
- Machine, Supervisor, and User modes, v1.11
- Hypervisor extension, v1.0
- Svnapot extension, v1.0
- Svpbmt extension, v1.0
- Svinval extension, v1.0
- CMO extension, v1.0
- Debug v0.14
- Smepmp extension v1.0
- Smstateen extension, v1.0
As a Spike extension, the remainder of the proposed Bit-Manipulation Extensions is provided under the Spike-custom extension name Xbitmanip. These instructions (and, of course, the extension name) are not RISC-V standards.
You can download Spike for RISC-V here
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