Imperas recently released a new ISS specifically for use in developing tests and compliance suites for RISC-V processors. It is free from GitHub

 

The riscvOVPsimISS is an ideal starting point for an embedded software development project.

 

RiscvOVPsim allows the development and debug of code for the target RISC-V processor on an x86 host PC with the minimum of setup and effort. It simply requires the cross compilation of your application and running riscvOVPsim with an argument to specify the name of the application object.

 

Used by application software engineers who need to create software binaries for RISC-V permitted configurations and variants, but who do not need platform components – riscvOVPsim works with a standard GDB debugger and GUI which makes it very easy to get started with full source code interactive debugging.

 

Test engineers can use riscvOVPsim in a regression test environment as it can be used in batch/scripted environments as well as being used interactively.

 

 

riscvOVPsim is also used by the RISC-V Foundation’s Compliance working group in the RISC-V compliance test suite and framework, the latest version is available on GitHub: https://github.com/riscv/riscv-compliance

 

riscvOVPsim – detailed features

Released to run in x86 64 bit Windows/Linux environments.

  • includes a free to use simulation license from Imperas, which supports commercial as well as academic use. The RISC-V open source model is licensed under the Apache 2.0 license.
  • includes the full publicly released Imperas OVP Fast Processor Models of RISC-V which covers all the single core 32/64 bit RISC-V permitted configurations and variants.
  • includes a GDB debugger
  • configurable trace subsystem to provide instruction and register tracing
  • loads .elf file binaries directly
  • allows one instance of a single CPU with full memory construction
  • uses built in semi-hosting to support library functions such as printf and fopen, and can access host native resources
  • can be run interactively or in script/batch mode for regression testing
  • includes Imperas Just-In-Time (JIT) Code Morphing high performance CPU simulator technology
  • works with Eclipse/CDT GUI

 

You can download the Imperas ISS here

 

You can also check our Imperas website for the complete verification suite and tooling here