Ibex is a production-quality open source 32-bit RISC-V CPU core written in SystemVerilog. The CPU core is heavily parametrizable and well suited for embedded control applications. Ibex is being extensively verified and has seen multiple tape-outs. Ibex supports the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions.

 

The block diagram below shows the small parametrization with a 2-stage pipeline.

 

 

Ibex was initially developed as part of the PULP platform under the name “Zero-riscy”, and has been contributed to lowRISC who maintains it and develops it further. It is under active development.

 

You can download the Ibex core here