RSD is a 32-bit RISC-V out-of-order superscalar processor core. RSD is very fast due tospeculative load/store execution and dynamic memory disambiguation features, while it is very compact and can be synthesized for small FPGAs.
Features of RSD
- ISA
- Support RV32IM
- Support Zephyr applications
- Microarchitecture
- 2-fetch front-end and 5-issue back-end pipelines
- Up to 64 instructions are in-flight.
- A high-speed speculative instruction scheduler with a replay mechanism
- Speculative OoO load/store execution and dynamic memory disambiguation
- Non-blocking L1 data cache
- Support AXI4 bus
- Implementation
- Written in SystemVerilog
- Can be simulated with Mentor Modelsim/QuestaSim, Verilator, and Vivado
- Can be synthesized with Synopsys Synplify and Design Compiler
- Design Compiler support is experimental
- We are preparing the support for Xilinx Vivado.
- Can run on a Xilinx Zynq board
- Avnet Zedboard
- FPGA optimized RAM structures
You can download RSD here
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