SCR1 is an open-source and free to use RISC-V compatible MCU-class core, designed and maintained by Syntacore. It is industry-grade and silicon-proven (including full-wafer production), works out of the box in all major EDA flows and Verilator, and comes with extensive collateral and documentation.
Key features
- Open sourced under SHL-license (see LICENSE file) – unrestricted commercial use allowed
- RV32I or RV32E ISA base + optional RVM and RVC standard extensions
- Machine privilege mode only
- 2 to 4 stage pipeline
- Optional Integrated Programmable Interrupt Controller with 16 IRQ lines
- Optional RISC-V Debug subsystem with JTAG interface
- Optional on-chip Tightly-Coupled Memory
- 32-bit AXI4/AHB-Lite external interface
- Written in SystemVerilog
- Optimized for area and power
- 3 predefined recommended configurations
- A number of fine-tuning options for custom configuration
- Verification suite provided
- Extensive documentation
You can download the SCR1 core here
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