RISCV-DV is a SV/UVM based open-source instruction generator for RISC-V processor verification. It currently supports the following features:

 

  • Supported instruction set: RV32IMAFDC, RV64IMAFDC
  • Supported privileged mode: machine mode, supervisor mode, user mode
  • Page table randomization and exception
  • Privileged CSR setup randomization
  • Privileged CSR test suite
  • Trap/interrupt handling
  • Test suite to stress test MMU
  • Sub-program generation and random program calls
  • Illegal instruction and HINT instruction generation
  • Random forward/backward branch instructions
  • Supports mixing directed instructions with random instruction stream
  • Debug mode support, with fully randomized debug ROM
  • Instruction generation coverage model
  • Handshake communication with testbench
  • Support handcoded assembly test
  • Co-simulation with multiple ISS : spike, riscv-ovpsim, whisper, sail-riscv

 

You can download the RISC-DV veirification tool here