This is a course from Udemy on how to design a RISC-V SOC
What you’ll learn
- Students will be able to build and configure their own SoC (System-On Chip)
- Students will be able to create their own defition of GPIO
- Understand decision making process, analog peripheral (ADC, DAC), digital peripheral (UART, flash controller), memory mapping, pad-frame, level-shifters, GPIO
- Finally, plan your SoC
Requirements
- A Linkedin login ID
- Knowledge on RISC-V is nice to have, but not must to have
- Digital design concepts and a bit of verilog syntax is nice to have
Description
Building a chip is like building a city. This was the mantra with which we started our company in 2011. Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from “chip designing” to “chip planning”.
Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.
Do you want to know what it is like to build a city? Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.
You can enroll in this course here
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