The focus of the HARV processor core is harsh environments. It implements the integer instruction-set of the RISC-V specification (RV32I), except system calls. To provide reliability for harsh environments, we implement the fault tolerance techniques TMR (Triple-Modular Redundancy) and Hamming code to the different parts of the processor. These techniques improve the reliability by mitigating or correcting errors caused by the single-event effects SEU (Single-Event Upset) and SET (Single-Event Transient).

 

HARV is being developed in partnership between the LEDS – Laboratory of Embedded and Distributed Systems and the LIRMM – Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier.

 

The HARV was first introduced by a paper published at the IEEE DTIS 2020.

You can download HARV here