Raven is using a very popular 32-bit RISC-V core (PicoRV32) developed by Clifford Wolf, a well-known open source champion. The core was previously proven with an FPGA implementation and Raven is the first SoC built with it. The system integrator is our own Tim Edwards, another champion in the open source domain. Included below is a 15s video showing the wakeup, key features and a link to high-level datasheet.

 

The requirements for simulating the Raven chip are: iverilog (iverilog.icarus.com), and the RISC-V gcc configured for the RISC-V options used by the picoRV32 processor design. The best way to obtain the correct gcc cross-compiler is to install the picoRV32 source from github (https://github.com/cliffordwolf/picorv32).

 

RAVEN-PICORV32

 

Raven is now published in efabless marketplace for designers and partner companies to clone and customize starting from a silicon-proven point.

 

Features:
  • RISC-V CPU (PicoRV32)
  • SRAM 32×1024
  • 100 MHz clock rate
  • Programmable clock source
  • 16 channels GPIO
  • 2 ADCs
  • 1 DAC
  • 1 Comparator
  • Over-temperature alarm
  • 100 kHz RC oscillator
  • Programmable functions on GPIO outputs
  • Programmable interrupts on GPIO inputs

 

You can get the Raven core here