ReonV is a modified version of the Leon3, a synthesizable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to implement the RISC-V RV32I ISA.

 

Simply speaking, ReonV is a RV32I version of the Leon3 processor which is provided as part of the GRLIB IP Library on GPL license by Cobham Gaisler AB. ReonV changed the Leon3 7-stage integer pipeline from SPARC to RISC-V, maintaining all other IP cores and resources provided by GRLIB IP Library untouched. The aim is to provide all the support to synthesis and peripherals Leon3 has to a RISC-V processor.

 

You can check out the ReonV core here