Based on Chisel3, Rift2Core is a 9-stage, N-issue(Configurable), out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.

 

You can complete the deployment of compilation and test environment of Rift2Core following the steps below:

  • Setup Repo
  • Setup sbt
  • Setup verilator and gtkwave
  • Compile chisel3 to verilog
  • Compile Model of Rif2Chip
  • Test a single ISA with waveform
  • Test all ISA without waveform

Also available is a Docker-Image mainly for CI, which can also be used for compiling and testing.

 

You can get the Rift2Core core for free here